A Floating-Point VLSI Chip for the TRON Architecture: An Architecture for Reliable Numerical Programming

A Floating-Point VLSI Chip for the TRON Architecture: An Architecture for Reliable Numerical Programming
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About A Floating-Point VLSI Chip for the TRON Architecture: An Architecture for Reliable Numerical Programming
A Floating-Point VLSI Chip for the TRON Architecture: An Architecture for Reliable Numerical Programming- Abstract of paper on Gmicro/FPU (floating-point unit), defines 23 coprocessor instructions; with references, purchase option. [IEEE Micro]
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